1. Technical Field
The present disclosure relates to Phase-Locked Loops (PLLs) that make use of a supply-regulated Voltage-Controlled Oscillator (VCO) architecture.
2. Background Information
A supply-regulated Phase-Locked Loop (PLL) generally involves a Voltage-Controlled Oscillator (VCO) whose oscillating frequency is determined and controlled by an input control signal such as a control voltage signal. FIG. 1 (Prior Art) is a diagram of one such PLL 1. PLL 1 involves a Phase-to-Frequency Detector (PFD) 2, a Charge Pump (CP) 3, a loop filter 4, a supply regulation control loop circuit 5, a bypass capacitor 6, an oscillator 7, and a feedback divider 8. The supply regulation control loop circuit 5, the oscillator 7, and the bypass capacitor 6 together form a VCO 9. Supply regulation control loop circuit 5 involves an operational amplifier 10 and a P-channel field effect transistor M1 11 interconnected as illustrated. PFD 2 compares the phase of a reference signal FREF 12 and the phase of a feedback signal FDIV 13 and outputs UP pulses or DN pulses depending on whether the phase of FDIV leads or leads or lags the phase of FREF. Charge pump 3 converts the pulses into a control current signal ICP 14. Control signal ICP 14 is filtered by loop filter 4 and is converted into a control voltage signal VCTRL 15. The supply regulation control loop circuit 5, the oscillator 7, and the bypass capacitor 6 together constitute a VCO because the oscillating frequency of the output signal VCO_OUT 16 of the oscillator is a function of the input control voltage signal VCTRL 15. The VCTRL signal is sometimes referred to as a fine tune signal and is denoted VTUNE. Oscillator 7 is an oscillator whose output signal VCO_OUT 16 has a frequency that is fairly proportional to the supply current ICTRL 17 supplied to the oscillator. If signal VCTRL 15 increases, then the control current ICTRL 17 supplied to the oscillator increases, and this causes the oscillating frequency of the oscillator output signal VCO_OUT 16 to increase. Similarly, if signal VCTRL 15 decreases, then the control current ICTRL 17 supplied to the oscillator decreases, and this causes the oscillating frequency of the oscillator output signal VCO_OUT 16 to decrease. The control loop operates to maintain the frequency and phase of VCO_OUT such that the phase and frequency of signal FDIV 13 as received by PFD 2 matches the frequency and phase of signal FREF 12 as received by PFD 2. When the PLL is in this state, the PLL is said to be in lock.
It is desired that signal ICTRL 17 be a function of the control voltage signal VCTRL 15 and only a function of the control voltage signal VCTRL 15. Unfortunately, there is often noise on the supply voltage VDD_NOISY at supply voltage conductor 18. This noise should not be allowed to affect oscillator operation. The supply regulation control loop circuit 5 operates to keep signal ICTRL 17 a function of control signal VCTRL 15, but the supply regulation control loop circuit has a limited bandwidth. High frequency noise VDD_NOISY that is of a frequency outside the bandwidth of the control loop can cause high frequency variations in the drain current of transistor M1 11. Accordingly, bypass capacitor 6 is provided to shunt such high frequency noise to ground so that oscillator 7 is not unduly affected by such noise.
FIG. 2 (Prior Art) illustrates a problem with the circuit of FIG. 1. Line 19 indicates how supply noise sensitivity varies as a function of frequency. Voltage VS is the regulated supply voltage on the common node at the supply current input lead of oscillator 7 and VDD_NOISY is the noisy supply voltage on supply voltage conductor 18. The supply regulation loop from the control voltage signal VCTRL 15 to the regulated supply voltage VS has two poles at frequencies F1 and F2. The dominant pole at frequency F1 is due to the parasitic capacitance associated with transistor M1 11 and the output resistance of operational amplifier 10. This dominant pole determines the upper frequency bound where the operational amplifier supply regulation control loop circuit no longer rejects supply voltage noise well. The operational amplifier supply regulation control loop rejects power supply noise relatively well for frequencies below frequency F1, but does not reject power supply noise so well for frequencies above frequency F1. F1 is approximately equal to ½π(ROUT*CP), where ROUT is the output resistance of the operational amplifier 10, and where CP is the effective parasitic capacitance associated with transistor M1.
There is a non-dominant pole at frequency F2 due to the bypass capacitor 6 and the effective resistance of the oscillator 7. Above frequency F2, the bypass capacitor 6 works relatively well in shunting supply voltage noise to ground but below the frequency F2 the bypass capacitor 6 does not shunt noise very well. Freg is the unity gain bandwidth of the operational amplifier. F2 is approximately ½π(RVCO*CBYCAP), where RVCO is the effective resistance of the ring oscillator, and where CBYCAP is the capacitance of the bypass capacitor 6. In order to achieve good power supply rejection at low frequencies, the gain of operational amplifier 10 is generally maximized which results in ROUT>>RVCO. This makes F1<F2 and results in peaking 21 in the supply noise sensitivity transfer function (VS(s)NDD_NOISY(s)) as shown in FIG. 2.
As shown in FIG. 2, there is a gap 20 between F1 and F2 where the overall supply regulation circuit does not reject supply voltage noise well. This poor rejection of voltage supply noise is referred to as supply noise sensitivity “peaking” and is represented by arrow 21. The frequency F1 of the dominant pole is determined by parasitic capacitances of transistor M1 11 such as the source-to-gate parasitic capacitance 22 and the gate-to-drain parasitic capacitance 23 and the output resistance of operational amplifier 10. Making these parasitic capacitances smaller would allow the frequency F1 of the dominant pole to be increased, and these parasitic capacitances could be made smaller by making transistor 11 smaller. Unfortunately, transistor 11 must be large enough to supply the required current signal ICTRL 17 to the oscillator 7. The output resistance of the operational amplifier 11 could be decreased to increase the frequency F1 of the dominant pole as well, but this would increase the supply noise sensitivity at low frequencies. For such reasons, the frequency F1 of the dominant pole cannot generally be increased as much as desired to close the F1 to F2 gap 20. Secondly, the frequency F2 due to the bypass capacitor 6 cannot generally be decreased enough to eliminate the F1 to F2 gap 20. One limit on how low F2 can be is the amount of integrated circuit area required to realize a larger bypass capacitor. Another limit is stability of the supply regulation loop. If the non-dominant pole gets too close in frequency to frequency of the dominant pole of the supply regulation loop, then the stability of the supply regulation loop is degraded.
FIG. 3 (Prior Art) is a diagram of a PLL circuit 24 that overcomes some of the problems of the circuit of FIG. 1. A replica 25 of the oscillator 7 has a low frequency current-voltage characteristic (I-V characteristic) similar to the I-V characteristic of oscillator 7. Replica 25 in this case involves a diode-connected P-channel transistor 26 that is connected in parallel with a diode-connected N-channel transistor 27. These transistors are sized such that the I-V characteristic of replica 25 is similar to the I-V characteristic of oscillator 7. In circuit 24 of FIG. 3, the gate of transistor M1 11 of the supply regulation control loop circuit 5 is tied to the gate of a second transistor M2 28. Accordingly, the supply regulation control loop circuit 5 can regulate using transistor M1 11, and can at the same time also supply current ICTRL 29 to the main oscillator 7 via a transistor M2 28. The bypass capacitor 6 is no longer in the operational amplifier supply regulation control loop 5. Hence, the size of bypass capacitor 6 can be increased to mitigate supply noise sensitivity peaking without affecting the stability of the supply regulation loop.
FIG. 4 (Prior Art) is a diagram that illustrates a problem with the circuit of FIG. 3. Dashed line 19 indicates how supply noise sensitivity changes as a function of frequency in the circuit of FIG. 1, whereas solid line 31 indicates how supply noise sensitivity changes as a function of frequency in the circuit of FIG. 3. Vertical dashed lines 32, 33 and 34, indicate F1, F2 and Freg of the circuit of FIG. 1, respectively, whereas vertical dashed lines 35, 36 and 37 indicate F1, F2 and Freg of the replica circuit of FIG. 3, respectively. As compared to the circuit of FIG. 1, the frequency F1 is reduced due to the additional parasitic capacitances associated with transistor M2. As compared to the circuit of FIG. 1, the frequency F2 in the replica circuit can be decreased because the capacitor 6 is outside the supply regulation loop and therefore can be made larger. Because F2 can be made very close to or less than F1, there is little or no supply noise sensitivity peaking. The I-V characteristic of the replica 25 may not, however, exactly match the I-V characteristics of the oscillator 7. This imprecise matching serves to increase supply noise sensitivity at low frequencies as illustrated. Arrows 39 represent the increased supply noise sensitivity at low frequencies that is largely due to imprecise matching of the replica and the oscillator.
Another problem associated with the circuit of FIG. 3 is that the low frequency noise (such as 1/f noise) from the replica transistors themselves 26 and 27 will cause low frequency variations in ICTRL. This can increase the close-in phase noise of the ring oscillator 7 which is an important specification in certain applications. The noise contribution from the replica transistors 26 and 27 will cause a variation in VS. The supply regulation control loop 5 will try to compensate for this variation by applying a corrective voltage to the gates of transistors M1 and M2. However, the corrective voltage applied to gate of transistor M2 will actually cause undesirable low frequency variations in ICTRL. This is because the noise sources in this case are the replica devices themselves unlike the supply noise which is common to both the replica and the oscillator. This is a problem only at frequencies within the bandwidth of the supply regulation control loop 5. At high frequencies, the bypass capacitor 6 will shunt the noise currents to ground.
FIG. 5 (Prior Art) is a simplified diagram that illustrates the low frequency noise problem with the circuit of FIG. 3. The current source symbol 38 represents the noise current INOISE_REPLICA due to replica 25. This noise current has two components, a low frequency component INOISE_REPLICA(LF) and a high frequency component INOISE_REPLICA(HF). The supply regulation control loop involving operational amplifier 10 supplies the total current IREPLICA+INOISE_REPLICA. ICTRL is the desired control current of magnitude K*IREPLICA as supplied to the oscillator 7, where transistor M2 is K times larger than transistor M1. Because transistor M2 is K times larger than transistor M1, the noise current INOISE_REPLICA is multiplied by transistor M2 such that the current supplied by transistor M2 is ICTRL+K*INOISE_REPLICA. Although bypass capacitor 6 can shunt high frequency noise to ground, it does not shunt low frequency noise to ground. Bypass capacitor 6 shunts the K*INOISE_REPLICA(HF) component of current output by transistor M2 to ground, leaving the remaining K*INOISE_REPLICA(LF) to flow into the oscillator 7. This low frequency component of the magnified replica noise causes jitter and phase noise in the signal output by oscillator 7.